ES390: Digital VLSI Design Assignment
Design of a CMOS 4--bit counter using Tanner Tools Software To be completed in weeks 4, 5 and 6
In this assessed exercise you will be designing a 4 bit counter with reset logic. In order to complete this task you will first design a 4 bit incrementer based on half--adder design. The incrementer design will then provide the basis for the design of a 4 bit counter.
There are three laboratory sessions (weeks 4, 5 and 6) allocated for the completion of this assignment. You are required to submit your designs (ES390A1) and a full report (ES390A2) (containing all the schematics, layouts, and simulation results) using the electronic submission of assignments system on the web. Credit allocated for both assignments is 25%.
Learning outcomes: By successfully completing this exercise you will demonstrate understanding of the role, and skills in the use of Computer Aided Design Software for VLSI. You will also be able to appreciate the properties of VLSI technology and its effect on logic implementation, optimisation and system design.
1. A Half Adder cell can be constructed using NAND, ANDOR and INV (designed in weeks 1 --3) as shown in Figure 1 below:
As before, you will be using Tanner Tools v16.03 for your designs.
Create a new topcell, hadd, for Half Adder circuit that uses NAND2, INV and ANDOR as subcells (use the instance command to implement this design). Design hadd such that its external connections appear as follows:
The above layout will enable hadd cells to abut each other horizontally, such that the AB(carry) output connects the A input of the next cell, and Vdd and GND similarly. You should ensure that you DO NOT paint over instances of subcells unless absolutely necessary.
Once completed, check that the functionality of your half adder (both schematic and layout) is correct using T--SPICE.
2. Design a 4 bit incrementer by using four half--adders in the following arrangement
Save the design as inc4. Simulate and fully verify your design with T--SPICE and W--EDIT.
3. Use the above incrementer, shift registers (similar to the one shown in Figure 5) and some additional logic to make a 4 bit counter with synchronous reset. The additional logic should force the counter outputs to zero when the reset signal is active high.
4. Once completed, verify that the functionality of the complete 4 bit counter (both schematic and layout) is correct using T--SPICE.
5. Provide a full report (containing all the schematics, layouts, timing analysis, and simulation results including test vectors used).
Summary of assessment criteria for your design:
Design ES390A1 (12.5%)
Including completeness of design, efficient use of space, use of standard layout style.
Report ES390A2 (12.5%)
Including completeness of simulation, timing analysis, test vectors used, W_Edit traces.
Half adder 20 20
Incrementer 15 15
Reset logic 20 20
Shift register 20 20
counter 25 25
The VLSI design and report submission deadline (using the electronic submission of assignments system on the web) is Week 7.
N.B. submission after the deadline will attract the usual late penalties.
It is important that the valid cell names such as NAND, HADD, INVERTER, INCREMENTER, etc. must be used. Cells named Cell0, Cell1 etc. will not be marked.
Dr M Cole and Professor J Gardner